The present invention relates to techniques for semiconductor processing.
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Integrated circuits are typically fabricated from semiconductor wafers in a process consisting of a sequence of processing steps. This process, usually referred to as wafer fabrication or wafer fab, includes such operations as oxidation, etch mask preparation, etching, material deposition, planarization and cleaning.
A summary of an aluminum gate PMOS (p-channel metal oxide semiconductor transistor) wafer fab process 40 is schematically shown in FIG. 1, illustrating major processing steps 41 through 73, as described in W. R. Runyan et al., Semiconductor Integrated Circuit Processing Technology, Addison-Wesley Publ. Comp. Inc., p.48, 1994. Each of these major processing steps typically include several sub steps. For example, a major processing step such as metallization to provide an aluminum layer by means of sputter deposition in a wafer fab chamber is disclosed in U.S. Pat. No. 5,108,570 (R. C. Wang, 1992). This sputter deposition process is schematically shown in sub steps 81 through 97 of process 80, see FIG. 2.
FIGS. 1 and 2 show sequential wafer fab processes. It is also known to utilize wafer fab sub systems which provide parallel processing steps. Such sub systems typically include one or more cluster tools. A cluster tool as defined herein includes a system of chambers and wafer handling equipment wherein wafers are processed in the cluster tool chambers without leaving a controlled cluster tool environment such as vacuum. An example of a cluster tool is disclosed in U.S. Pat. No. 5,236,868 (J. Nulman, 1993) which employs a vacuum apparatus having a central chamber and four processing chambers. A wafer handling robot in the central chamber has access to the interior of each the processing chambers in order to transfer wafers from the central chamber into each of the chambers while keeping the wafers in a vacuum environment. In one example, wafers in the ""868 cluster are first transferred for processing to a cleaning chamber, then to a PVD (physical vapor deposition) chamber, followed by transfer to an annealing chamber and subsequently to a degassing chamber, thus utilizing a sequential process. It is also known to use cluster tools such as those disclosed in the ""868 patent to process wafers in chambers which are used in parallel. For example, if a slow processing step is followed by a fast processing step, three chambers can be used in parallel for the slow process while the fourth chamber is used for the fast process.
It is well known to those of ordinary skill in the art that one or more processing parameters of a typical wafer fab process step need to be controlled within a relatively narrow range in order to obtain a product which has the desired characteristics. For example, U.S. Pat. No. 5,754,297 (J. Nulman, 1998) discloses a method and apparatus for monitoring a deposition rate during wafer fab metal film deposition such as sputtering. The ""297 patent teaches that the metal deposition rate decreases with increasing age of the sputter target if the input sputter power level is maintained at a constant level. As a consequence, critical processing characteristics, such as the metal deposition rate, may vary from run to run for a given wafer fab processing chamber in ways that can affect the yield and quality of devices processed in that chamber. As disclosed in the ""297 patent, the deposition system can be more readily maintained near desired levels when processing variables, such as the power input to the sputtering source, are adjusted in response to observed variations in the metal deposition processing characteristics. This requires in-situ measurement of processing characteristics, using for example a deposition rate monitor based on the optical attenuation of light passing through the deposition environment, thereby detecting the rate at which material is flowing from the deposition source to the deposition substrate, as described more fully in the ""297 patent.
Advances in semiconductor materials, processing and test techniques have resulted in reducing the overall size of the IC circuit elements, while increasing their number on a single body. This requires a high degree of product and process control for each processing step and for combinations or sequences of processing steps. It is thus necessary to control impurities and particulate contamination in the processing materials such as process gases. Also, it is necessary to control processing parameters such as temperature, pressure, gas flow rates, processing time intervals and input sputter power, as illustrated in the ""570 and ""297 patents. As illustrated in FIGS. 1 and 2, a wafer fab includes a complex sequence of processing steps wherein the result of any particular processing step typically is highly dependent on one or more preceding processing steps. For example, if there is an error in the overlay or alignment of etch masks for interconnects in adjacent IC layers, the resulting interconnects are not in their proper design location. This can result in interconnects which are packed too closely, forming electrical short defects between these interconnects. It is also well known that two different processing problems can have a cumulative effect. For example, a misalignment of interconnect etch masks which is not extensive enough to result in an electrical short, can still contribute to causing an electrical short if the process is slightly out of specification for allowing (or not detecting) particulate contamination having a particle size which would not have caused an electrical short if the interconnect masks had been in good alignment.
Processing and/or materials defects such as described above generally cause a reduced wafer fab yield, wherein the yield is defined as the percentage of acceptable wafers that are produced in a particular fab. In-process tests and monitoring of processing parameters are utilized to determine whether a given in-process product or process problem or defect indicates that intervention in the process run is necessary, such as making a processing adjustment or aborting the run. Consequently, product and process control techniques are used extensively throughout a wafer fab. When possible, yield problems are traced back to specific product or processing problems or defects to ultimately improve the yield of the wafer fab. High yields are desirable for minimizing manufacturing costs for each processed wafer and to maximize the utilization of resources such as electrical power, chemicals and water, while minimizing scrap re-work or disposal.
It is known to use SPC (statistical process control) and SQC (statistical quality control) methods to determine suitable wafer fab control limits and to maintain the process within these limits, see for example R. Zorich, Handbook Of Quality Integrated Circuit Manufacturing, Academic Press Inc., pp. 464-498, 1991. SPC and SQC methodologies suitable for a wafer fab include the use of control charts, see for example R. Zorich at pp. 475-498. As is well known to those of ordinary skill in the art, a control chart is a graphical display of one or more selected process or product variables, such as chamber pressure, which are sampled over time. The target value of a particular variable and its upper and lower control limits are designated on the chart, using well known statistical sampling and computation methods. The process is deemed out of control when the observed value of the variable, or a statistically derived value such as the average of several observed values, is outside the previously determined control limits. Control limits are typically set at a multiple of the standard deviation of the mean of the target value, such as for example 2"sgr" or 3"sgr". The target value is derived from a test run or a production run which meets such wafer fab design criteria as yield, process control and product quality. SPC and SQC are considered synonymous when used in the above context, see R. Zorich at p. 464.
Effective wafer inventory management is necessary for maintaining inventories of unprocessed or partly processed wafers at a minimum and thereby minimizing the unit cost of the semiconductor devices which are produced in the wafer fab. Minimizing inventories of wafers in process also has a wafer yield benefit because it is well known that the longer wafers are in the process, the lower their yield. Wafer inventory management typically uses scheduling techniques to maximize equipment capabilities in view of the demand for processed wafers, for example by scheduling parallel and series processing steps to avoid processing bottlenecks. Effective inventory management of a wafer fab also requires a low incidence of bottlenecks or interruptions due to unscheduled down times which can for example be caused by unscheduled maintenance, interruptions resulting from processing parameters which are outside their specified limits, unavailability of required materials such as a process gas, unavailability of necessary maintenance replacement parts, unavailability of a processing tool such as a chamber, or electrical power interruptions.
Many components or sub-systems of a wafer fab are automated in order to achieve a high degree of processing reliability and reproducibility and to maximize yields. Wafer fab tools such as chambers are typically controlled by a computer using a set of instructions which are generally known as a recipe for operating the process which is executed by the tool. However, it is recognized that a high degree of automation wherein various processes and metrologies are integrated, is difficult to achieve due to the complexity and inter dependency of many of the wafer fab processes, see for example Peter van Zandt, Microchip Fabrication, 3rd ed., McGraw-Hill, pp. 472-478, 1997.
It is well known to those of ordinary skill in the art that the functions of semiconductor manufacturing equipment, including for example a wafer fab, can be defined in basic equipment states such as the six states schematically illustrated in FIG. 3, see SEMI E10-96, Standard For Definition And Measurement Of Equipment Reliability Availability, And Maintainability (RAM), published by Semiconductor Equipment and Materials International (SEMI), pp. 1-23, 1996. The semiconductor industry typically uses these six equipment states to measure and express equipment RAM (reliability availability and maintainability), based on functional equipment issues which are independent of who performs the function. These six basic equipment states include non-scheduled time 102 (FIG. 3), unscheduled downtime 104, scheduled downtime 106, engineering time 108, standby time 110 and productive time 112. Non-scheduled time 102 represents the time period wherein the equipment is not scheduled to be used, for example unworked shift. Unscheduled downtime 104 concerns time periods wherein the equipment is not in a condition to perform its intended function, e.g. during equipment repair. Scheduled downtime 106 occurs when the equipment is capable of performing its function but is not available to do this, such as process setup or preventive maintenance. Engineering time 108 concerns the time period wherein the equipment is operated to conduct engineering tests, for example equipment evaluation. Standby time 110 is a time period wherein the equipment is not operated even though it is in a condition to perform its intended function and is capable of performing its function, for example no operator is available or there is no input from the relevant information systems. Productive state 112 represents the time period wherein the equipment is performing its intended function, such as regular production and rework.
Total time period 114, see FIG. 3, is the total time during the period being measured; this includes the six equipment states 102, 104, 106, 108, 110 and 112. Operations time 116 concerns the total time period of states 104, 106, 108, 110 and 112. Operations time 116 includes equipment downtime 118 consisting of states 104 and 106, and equipment uptime 120. Equipment uptime 120 includes engineering time 108 and manufacturing time 122 which consists of standby time 110 and productive time 112.
FIGS. 4 and 5 provide more detailed schematic illustrations of the six equipment states shown in FIG. 3, see SEMI E10-96, at pp. 1-6. As depicted in FIG. 4, total time 114 consists of non-scheduled time 102 and operations time 116. Non-scheduled time 102 includes unworked shifts 130, equipment installation, modification, rebuilding or upgrading 132, off-line training 134 and shutdown or start-up time period 136. Operations time 116, as schematically illustrated in FIG. 5, consists of equipment downtime 118 and equipment uptime 120. Equipment downtime 118 consists of unscheduled downtime 104 and scheduled downtime 106. Unscheduled downtime 104 includes downtime for maintenance delay 140, repair time 142, changing consumables/chemicals 144, out of specification input 146 or facilities related downtime 148. Scheduled downtime 106 concerns downtime for maintenance delay 150, production test 152, preventive maintenance 154, changing consumables/chemicals 156, setup 158 or facilities related 159.
Equipment uptime 120, depicted in FIG. 5, consists of engineering time 108 and manufacturing time 122. Engineering time 108 includes process experiments 160 and equipment experiments 162. Manufacturing time 110 consists of standby time 110 and productive time 112. Standby time 110 includes time during which there is no operator 180, no product 182, no support tool 184 or when an associated cluster module is down 186. Productive time 112 concerns a time period during which there is regular production 190, work for a third party 192, rework 194 or an engineering run 196. The various equipment states as described in connection with FIGS. 3-5 provide a basis for communicating and evaluating RAM related equipment information in the semiconductor industry. RAM related equipment information includes topics which are well known to those of ordinary skill in the art such as: equipment reliability, equipment availability, equipment maintainability and equipment utilization, see for example SEMI E10-96 at pp. 6-11.
Accordingly, a need exists for methods and techniques which provide improved process control, quality, yield and cost reduction. Also, there is a need to integrate the equipment time states to provide enhanced process scheduling and improved utilization of processing equipment.
The present invention provides novel techniques for semiconductor processing, particularly for wafer manufacturing. These novel techniques provide the needed improvements in process control, quality, yield, equipment scheduling and cost reduction.
In one embodiment of the present invention, a novel delta analysis technique is employed to determine if there are significant processing or performance differences between two semiconductor processing runs using the same recipe in a tool such as a wafer fab chamber. Processing parameter or metrology data of the first run are plotted versus time to obtain a graph of data, such as gas flow rate, against time. A similar graph is prepared using data from the second processing run. The graphs are overlayed in a synchronized manner, e.g. the graphs are overlayed such that they start at the same time event, such as process startup. The data of one of the overlayed graphs are subtracted from the data of the other graph thereby forming a novel delta graph. Computer implemented delta graph analysis facilities the identification, analysis and trouble-shooting of semiconductor processing and/or performance problems, such as inconsistencies between processing runs
In another embodiment of the present invention, the same semiconductor processing recipe was used for production runs in two semiconductor processing chambers. Processing parameter or metrology data, such as chamber pressure, from one chamber were plotted versus time resulting in a graph of data versus time. A similar graph was prepared using data versus time from the other chamber. Subsequently, a synchronized graph overlay was prepared of the two graphs. The data of one of the overlayed graphs were subtracted from the data of the other graph, thus forming a delta graph. The delta graph was then used to determine of there were significant processing or performance differences between these chambers, when using this particular recipe. The computer implemented novel delta graph is utilized to identify, analyze or trouble-shoot performance differences between the chambers, thus leading to greater wafer fab processing uniformity, improved equipment utilization and improved wafer yield.
In yet another embodiment of the present invention, a quality control chart is prepared of a semiconductor processing run such as a test run or a standardized run. A quality control chart of a production run is then prepared using the same recipe in the same chamber. A synchronized overlay chart is prepared using the test run control chart and the production run control chart. A computer implemented delta graph is then prepared by subtracting the data of one chart from the other chart. The delta graph is analyzed to determine if there are significant differences between the production run and the test run, thus providing a method for analyzing the production run and improving wafer yield.
In still another embodiment of the present invention, a quality control chart for matching two wafer fab tools is prepared by executing a statistically significant number of process runs in these tools, using the same recipe in both tools. Computer implemented delta graphs are then constructed by plotting the same parameter from each tool versus time and subtracting the data of one tool from the data of the other tool. An analysis is then performed to determine which processing runs resulted in satisfactory tool matching performance. The delta graphs representing these runs are subsequently used to develop control limits, which can be used to evaluate the chamber matching performance of subsequent process runs.
In another embodiment of the present invention, computer integrated equipment time states are provided to facilitate manual and automatic scheduling of equipment functions and to provide an improved capability to respond to processing conditions. The time states can be enabled by a user through interactions with the computer through which the time states are integrated. In one embodiment of this invention, a service procedures module is provided which is automatically linked to one or more of these equipment time states and which is activated when one of these time states is enabled.
In yet another embodiment of the present invention, computer integrated equipment time states are integrated with the process which is executed in the equipment. Process/quality process control techniques of this process are linked to one or more equipment time states, causing the equipment to go off-line when the process is not operating within predetermined process/quality control limits.
In another embodiment of the present invention, the novel computer integrated time states are adapted to keep track of, and respond to, maintenance trigger events which automatically enable a preventive maintenance time state of a tool upon the occurrence of the trigger event. Examples of maintenance trigger events include a predetermined total wafer count and a predetermined total operating time of a tool.
Other embodiments of the present invention include digitally coded data structures stored in a memory. The data structures include delta graph methodologies and equipment time states of the present invention.